Spatial Reasoning at Silicon Scale: How Vision-Language Models Are Reshaping Chip Floorplanning

The Generalization Crisis in Automated Chip Design

The physical design of integrated circuits represents one of the most stubbornly difficult optimization problems in computer engineering. Macro placement, the strategic arrangement of large functional blocks on a silicon die, involves navigating a combinatorial explosion of possibilities while balancing performance, power, and area constraints. For decades, this task remained the exclusive domain of human experts who developed intuitive spatial reasoning through years of experience, enabling them to visualize promising regions of the chip canvas without exhaustive search.

Recent years have witnessed a surge of machine learning approaches promising to automate this expertise. Reinforcement learning methods like GraphPlace and imitation learning systems such as ChiPFormer have demonstrated impressive results within their training distributions. However, these approaches suffer from a critical limitation that has hindered their practical deployment: policies trained from scratch fail to generalize to unseen chip designs without additional fine-tuning or extensive retraining. This brittleness stems from the scarcity of training data in chip design and the vast diversity of architectural topologies across different integrated circuits.

In their recent paper, "See it to Place it: Evolving Macro Placements with Vision-Language Models," Uchendu et al. propose a fundamentally different approach that sidesteps the generalization problem entirely. Rather than training a specialized policy that must memorize specific design patterns, they leverage pretrained Vision-Language Models (VLMs) as zero-shot spatial reasoners. Their framework, VeoPlace, treats the chip canvas as a visual scene and uses a VLM to guide existing placement algorithms by suggesting promising subregions, achieving wirelength reductions exceeding 32% over prior learning-based methods on 9 of 10 benchmarks without requiring any model fine-tuning.

The VeoPlace Architecture: Visual Reasoning Meets Evolutionary Search

The technical innovation of VeoPlace lies in its hierarchical decomposition of the placement problem. At the high level, a VLM (specifically the public Gemini models) acts as a spatial planner that proposes constraints or regions of interest on the chip canvas. At the low level, an existing placer, whether learning-based like ChiPFormer or analytical like DREAMPlace, executes the actual placement within these constraints. This separation of concerns allows the system to combine the broad, transferable visual reasoning capabilities of foundation models with the specialized optimization competence of existing algorithms.

The framework operates through an iterative evolutionary loop that distinguishes it from simple one-shot prompting. The VLM maintains a history buffer containing visual representations of previously generated placements along with their evaluated metrics. By processing this history as an in-context sequence, the VLM performs a form of visual evolutionary optimization, proposing new constraints that combine and mutate successful patterns from prior iterations. This capability for in-context learning, processing dozens of prior placements simultaneously, exceeds what any individual human designer could reasonably track and analyze in working memory.

Critically, VeoPlace adapts its guidance strategy to the underlying placer type. For learning-based policies such as ChiPFormer, the VLM generates action masks that constrain the policy to specific canvas subregions. For analytical placers like DREAMPlace, it proposes soft anchor constraints that bias the numerical optimization toward particular spatial configurations. This flexibility allowed the authors to demonstrate improvements across fundamentally different algorithmic paradigms, including a 4.3% wirelength reduction on the ICCAD 2015 Superblue benchmarks when guiding DREAMPlace 4.3.0, and even larger gains when enhancing ChiPFormer on the ISPD 2005, ICCAD 2004, and Ariane benchmarks.

Why Visual Reasoning Matters for Silicon

The choice to use vision-language models rather than purely textual large language models reflects a deep insight about the nature of chip design. Human designers do not reason about floorplanning through netlist graphs or adjacency matrices alone; they look at the chip canvas. Spatial relationships, congestion hotspots, and macro clustering are inherently visual phenomena. By rendering the placement state as an image and processing it through a VLM, the system taps into representations learned from vast visual datasets, including geometric and spatial reasoning patterns that transfer naturally to the chip design domain.

This visual modality enables a form of transferable design intuition that pure reinforcement learning policies struggle to replicate. While RL agents must learn spatial reasoning from scratch within the narrow distribution of their training chips, VLMs bring prior knowledge about visual composition, proximity relationships, and geometric optimization that applies across domains. The paper demonstrates that this generalization capability is robust enough to improve placement quality on unseen benchmarks immediately, without the adaptation period required by previous learning-based methods.

However, the approach introduces new computational considerations. VLM inference is significantly more expensive than running a trained neural policy or analytical solver. In the context of chip design, where placement operations can already consume hours or days of compute time for complex designs, this overhead may be acceptable if the quality improvements translate to better final silicon performance. Nevertheless, the current evaluation focuses on relatively small benchmarks; the scalability of this approach to industrial-scale chips with thousands of macros and complex hierarchical constraints remains an open question requiring further investigation.

Implications and Future Directions

VeoPlace represents a broader shift in how we might deploy foundation models within engineering workflows. Rather than replacing specialized algorithms with end-to-end neural systems, the most promising near-term applications appear to be hybrid architectures where VLMs provide high-level reasoning and search guidance while domain-specific solvers handle the numerical heavy lifting. This mirrors the cognitive hierarchy in human design teams, where experienced architects provide constraints and guidance that junior designers or automated tools then implement.

The success of this approach raises intriguing questions about the future of electronic design automation. If VLMs can provide zero-shot improvements to existing placers, could similar frameworks enhance other stages of the design flow, such as timing optimization or routing? The evolutionary search mechanism demonstrated in VeoPlace, where the model iteratively refines proposals based on visual feedback, suggests a general template for VLM-guided optimization that could extend to other physical design tasks.

Yet significant challenges remain. The current implementation focuses primarily on wirelength optimization, while practical floorplanning must balance multiple competing objectives including power distribution, thermal management, and timing closure. How effectively VLMs can navigate these higher-dimensional trade-offs, particularly when the visual representation of the canvas may not immediately reveal timing-critical paths or thermal hotspots, will determine whether this approach scales to production environments.

Furthermore, the reliance on commercial VLM APIs introduces practical concerns regarding latency, cost, and reproducibility. As the field matures, we may see the development of smaller, open-source VLMs specifically trained on chip design visualizations, or the creation of efficient distillation techniques that capture the spatial reasoning capabilities of large models in faster, locally deployable systems.

The work of Uchendu and colleagues demonstrates that the gap between human and machine design intuition may be narrower than previously thought, provided we choose the right representational modalities. By allowing algorithms to literally "see" the chip canvas, we enable a form of spatial reasoning that transcends the limitations of task-specific training, pointing toward a future where foundation models serve as universal design assistants across the entire landscape of physical design.